This invention relates to digital computers, and more particularly to addressing of microinstruction memory in a CPU.
A high performance, microcoded, pipelined CPU is described by Sudhindra N. Mishra in "The VAX 8800 Microarchitecture", Digital Technical Journal, Feb. 1987, pp. 20-33. In a CPU of this type, pipelined microinstructions are used to control the execution and memory management operations, and an effort is made to assert a new microinstruction in every machine cycle, with a minimum of stalls or No-Op's, for maximum performance and efficiency. This goal of executing a new microinstruction in every machine cycle becomes more difficult, of course, as the clock speed goes up, and as the microcode becomes more complex, requiring many Call and Return type of microinstructions, where microaddresses are saved and recovered.
A stack is often used, as in the above-mentioned article, to save a current microaddress by a Push to Stack operation when a Call is executed, followed by a Pop from Stack operation when a Return is executed. However, in a highly pipelined CPU architecture, running at high clock speeds, some previously-used stack constructions could not implement consecutive Call and Return microinstructions, because of the time needed to decode the microinstructions, increment or decrement the stack pointer, read or write the stack, etc.
It is therefore the principal object of this invention to provide an improved method of addressing microinstructions in a CPU, particularly a high-speed pipelined CPU. Another object is to provide an improved stack memory configuration capable of high-speed operation. Another object is to provide an improved method of executing Call and Return type of instructions, as in microinstruction execution in a high-speed CPU or the like. A further object is to provide an improved method of executing stack Push and Pop operations, particularly by removing latency in a microinstruction address stack.